Manufactures take great care at each step of the integrated circuit (IC) manufacturing process to ensure that the quality of the device is as high as possible. The packaging (i.e., enclosure surrounding and connections to the IC) is no different. After the manufacture of the ICs, there remains the need to protect the individual IC dies from damage and to provide connections to other devices. These IC dies are typically electrically connected and mounted on a substrate core that often includes several patterned layers of conductive material, such as copper, located on either or both sides of the substrate core. Electrical connection is made through the substrate by way of patterned traces on copper layers located both above and below the core of the substrate. The area below the core also includes copper shielding ground planes that are present to promote good electrical performance.
As technology device sizes have continued to shrink, the industry has moved to thinner substrates in an effort to reduce the overall height of the packaged die. Using these thinner cores, however, can cause problems to arise during the reflow of the packaged device onto another device or substrate. Conventional packaging substrates typically have several layers located above and below the substrate core. These layers have copper traces formed thereon and are connected by vias that extend through the layers. Together, they form interconnect structures above and below the substrate core. The substrate core is typically comprised of an epoxy resin and fiberglass and has a different thermal expansion coefficient than do the layers on which the copper traces are formed. Due to the difference in the thermal expansion coefficients of these materials and the high temperatures associated with the reflow soldering process, the outer edges of these thinner substrates will often warp or curve up or down such that all of the solder joints or ball grid arrays (BGA) that are located on the solder joint or back side of the substrate do not make proper contact with the underlying substrate. This lack of full or complete connectivity leads to a defective or less than an optimum device.
Accordingly, what is needed in the art is a semiconductive device and method of manufacturer thereof that avoids the disadvantages associated with the above-discussed devices.